library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity seq_detector is 
port(clk,din:in std_logic;
	odd_t:out std_logic:='0';
	y:out std_logic
	);
end entity seq_detector;

architecture myfun of seq_detector is
	function oddt(din:std_logic_vector) return std_logic;
	
	function oddt(din:std_logic_vector) return std_logic is
	variable temp:std_logic;
	begin
	temp:='1';
	for i in 0 to 7 loop
		temp:=temp xor din(i);
	end loop;
	return temp;
	end function oddt;
	
	type state is(idle,one,two,three,four,five,six,seven,eight);
	signal ps,ns:state;
	constant rnum:std_logic_vector:="11010111";
	signal test:std_logic_vector(7 downto 0);
	
	
	begin

	p1:process(clk)is
	begin
	if(rising_edge(clk)) then 
		ps<=ns;
	end if;
	end process p1;
	
	p2:process(din,ps) 
	begin
	case ps is
		when idle=>
		y<='0';odd_t<='0';test(0)<=din;
			if din=rnum(0) then
				ns<=one;
			else
				ns<=idle;
			end if;
		when one=>
		y<='0';odd_t<='0';test(1)<=din;
			if din=rnum(1) then
				ns<=two;
			else
				ns<=idle;
			end if;
		when two=>
		y<='0';odd_t<='0';test(2)<=din;
			if din=rnum(2) then
				ns<=three;
			else
				ns<=idle;
			end if;
		when three=>
		y<='0';odd_t<='0';test(3)<=din;
			if din=rnum(3) then
				ns<=four;
			else
				ns<=idle;
			end if;
		when four=>
		y<='0';odd_t<='0';test(4)<=din;
			if din=rnum(4) then
				ns<=five;
			else
				ns<=idle;
			end if;
		when five=>
		y<='0';odd_t<='0';test(5)<=din;
			if din=rnum(5) then
				ns<=six;
			else
				ns<=idle;
			end if;
		when six=>
		y<='0';odd_t<='0';test(6)<=din;
			if din=rnum(6) then
				ns<=seven;
			else
				ns<=idle;
			end if;
		when seven=>
			y<='0';odd_t<='0';test(7)<=din;
			if din=rnum(7) then
				ns<=eight;
			else
				ns<=idle;
			end if;
		when eight=>
			y<='1';
			odd_t<=oddt(test);
			if din=rnum(0) then
				ns<=one;
				test(0)<=din;
			else
				ns<=idle;
			end if;
	end case;
	end process p2;

end architecture myfun;






































--library ieee;
--use ieee.std_logic_1164.all;
--use ieee.std_logic_arith.all;
--entity seq_detector is
-- port(clk,clr,din :in std_logic;
--      ab:out std_logic_vector(8 downto 0);
--      y:out std_logic;
--      op:out std_logic);
--end seq_detector;
--architecture behav of seq_detector is
-- function tt(din:std_logic_vector) return std_logic;
-- function tt(din:std_logic_vector) return std_logic is
--variable temp:std_logic;
--begin
--temp:='1';
--temp:=temp xor din(0);
--temp:=temp xor din(1);
--temp:=temp xor din(2);
--temp:=temp xor din(3);
--temp:=temp xor din(4);
--temp:=temp xor din(5);
--temp:=temp xor din(6);
--temp:=temp xor din(7);
--temp:=temp xor din(8);
--return temp;
--end function tt;
-- signal q:integer range 0 to 9;
-- signal d:std_logic_vector(8 downto 0);
--begin
--d<="110011000";
--p1:process(clk,clr)
--begin
--if clr='1'then q<=0;
--elsif clk'event and clk='1'then
--case q is
--when 0=>if din=d(8)then q<=1;
--else q<=0;end if;
--when 1=>if din=d(7)then q<=2;
--else q<=0;end if;
--when 2=>if din=d(6)then q<=3;
--else q<=0;end if;
--when 3=>if din=d(5)then q<=4;
--else q<=0;end if;
--when 4=>if din=d(4)then q<=5;
--else q<=0;end if;
--when 5=>if din=d(3)then q<=6;
--else q<=0;end if;
--when 6=>if din=d(2)then q<=7;
--else q<=0;end if;
--when 7=>if din=d(1)then q<=8;
--else q<=0;end if;
--when 8=>if din=d(0)then q<=9;
--else q<=0;end if;
--when others=> q<=0;
-- end case;
--end if;
--end process;
--p2:process(q)
--begin
--if q=9 then
--ab<="111111111";
--op<=tt(d);
--else
--ab<="000000000";
--end if;
--end process;
--end behav;